A conventional example of an insulator capacitor (to be referred to as “MIS capacitor” hereinafter) will be described with reference to FIG. 4. FIG. 4 shows an MIS capacitor device formed in, for example, a bipolar IC. For example, in FIG. 4, an N type epitaxial layer 122 is formed on a P type semiconductor substrate 121, and a silicon oxide layer or so-called LOCOS 123 formed by local oxidation of silicon and a device isolation diffusion layer 124 consisting of a P type diffusion layer and formed below the LOCOS 123, both of which layers become a device isolation region, are formed on the epitaxial layer 122. The device isolation diffusion layer 124 is formed to reach the semiconductor substrate 121. An N type semiconductor region 113 doped with N type impurities is formed on the epitaxial layer 122 defined by the device isolation region. A conventional MIS capacitor 101 is constituted by forming an opening portion 127 in a first interlayer insulating film 126 formed on a surface including a portion on the semiconductor region 113 with the semiconductor region 113 serving as a lower electrode, forming an insulating film (or a so-called dielectric film) 111 on the semiconductor region 113 facing this opening portion 127, and forming an upper electrode 112 of a polysilicon film on the insulating film 111. Further, a second interlayer insulating film 128 is formed to cover the upper electrode 112, a wiring 130 connected to the upper electrode 112 through an opening portion formed at a position in the second interlayer insulating film 128, which position corresponds to the upper electrode 112, is formed, and a wiring 131 connected to the lower electrode 113 through an opening portion formed at positions in the first and second interlayer insulating films 126 and 128, which positions correspond to the lower electrode 113, is formed.
In case of this MIS capacitor 101, the effective area thereof is determined according to the area of the opening portion 127 in the first interlayer insulating film 126, and the capacitance value thereof is determined according to the property and thickness of the insulating film (or dielectric film) 111 provided in the opening portion 127. Actually, however, even on the peripheral portion of the opening portion 127, a parasitic capacitance is generated between the upper electrode 112 and the lower electrode 113 with the first interlayer insulating film 126 and the insulating film (or dielectric film) 111 put between the upper and lower electrodes 112 and 113. This parasitic capacitance is added to an overall capacitance value proportionally to the peripheral length of the upper electrode 112 and that of the insulating film (or dielectric film) 111 on the peripheral portion of the opening portion 127.
Meanwhile, in case of the conventional semiconductor device, the applicable capacitance value range of the MIS capacitor is often in the order of 1 pF or more. It has hardly been assumed that capacitance values particularly in the applicable range of 100 fF or less are used. In particular, the required performance of the ordinary MIS capacitor is that the MIS capacitor has a capacitance value used frequently, i.e., a capacitance value per unit area as high as possible in a region in the order of pF to nF with a view of reducing the area of a circuit, a small area, high accuracy and high reliability. To meet this requirement, with an ordinary MIS capacitor formation technique, a silicon nitride (Si3N4) film [film thickness: about 20 nm to 50 nm] having a high dielectric constant and advantageous in reliability is often used as the dielectric film. The capacitance value per unit area of the MIS capacitor having the structure stated above is about 1 fF/μm2 to 3 fF/μm2.
In recent years, as signal processing is accelerated, the frequency of, for example, the circuit for an optical pickup of an optical disk (CD, DVD or the like) or a so-called PDIC (photodiode integrated circuit) becomes higher and an MIS capacitor in a region having a capacitance value of 100 fF or less is required as an MIS capacitor in the circuit.
Using the circuit configuration of the PDIC shown in FIG. 5, an example of using the MIS capacitor in a region having a capacitance value of 100 fF or less will be described. As shown in FIG. 5, an ordinary PDIC 140 consists of a photodiode 141 serving as a current source and a current-voltage conversion circuit (or so-called IV amplifier) 142. The photodiode 141 equivalently consists of a junction capacitance CPD and a photoelectric current iPD. The current-voltage conversion circuit 142 has a differential amplifier A. A predetermined bias voltage Vc is applied to a non-inverting input terminal of the differential amplifier A and a cathode of the photodiode 141 is connected to a inverting input terminal of the differential amplifier A through a wiring 143. A resistance Rt and a capacitance Ct are connected in parallel between the inverting input terminal of the differential amplifier A and the output terminal tOUT thereof from which an output voltage vO is obtained. Reference symbol CH denotes a wiring capacitance.
The frequency of the current-voltage conversion circuit 142 is expressed by Mathematical Expression 1 using the resistance Rt and the capacitance Ct shown in FIG. 5.f=1/(2π·Rt·Ct)  [Mathematical Expression 1]
For example, if an output voltage vO of 300 mV is necessary while the light receiving sensitivity S of the photodiode is 0.4 A/W and laser power P is 10 μW, the following relationship is obtained:Rt=vO/iPD=300e−3/(0.4×10e−6)=75000Ω=75 kΩ
As the read/write rates of optical disks (e.g., CD and DVD) are accelerated, demand for an improvement in the frequency characteristics of the PDIC 140 arises. For example, the PDIC 140 is required to have a cutoff frequency fc of about 100 MHz of a 10 times speed DVD.
If it is assumed that the cutoff frequency fc of the PDIC 140 is rate-controlled by the frequency characteristics of the current-voltage conversion circuit 142, the required MIS capacitance Ct is obtained using the above [Mathematical Expression 1] as follows:100 MHz=1/(2π·75kΩ·Ct)Ct=2.1e−14[F]=21[fF]
However, if the conventional MIS capacitor 101 is used, the ratio of a parasitic capacitance on the peripheral portion of the MIS capacitor to a capacitance formed by the effective area (or the area of the so-called opening portion 127) suddenly increases in a region having a capacitance value of 1 pF or less which is not supposed to fall in the applicable range. In other words, if the capacitance value is about 1 pF or less, the influence of the parasitic capacitance on the peripheral portion increases according to the increase of the peripheral length to area ratio of the MIS capacitor. Following this, the deterioration of the unevenness of the MIS capacitor resulting from the unevenness of the parasitic capacitance stated above (so-called controllability of capacitance value) becomes conspicuous. Taking an MIS capacitor in a currently conducted manufacturing process as an example, the unevenness of the MIS capacitor with a capacitance value of 10 fF is approximately ±50% (see a second MIS capacitor curve II shown in FIG. 2).
Under these circumstances, it is necessary to develop a semiconductor device having an MIS capacitor having a high capacitance value (e.g., in a region having a capacitance value exceeding 100 fF) and an MIS capacitor having a low capacitance value (e.g., in a region having a capacitance value of 100 fF or less) mounted on a common semiconductor substrate. In the development of the semiconductor device of this type, it is demanded that the unevenness of capacitance values is suppressed to be little within a practicable range while suppressing the occupied area of each MIS capacitor within a predetermined allowable range on an integrated circuit, and that the semiconductor device of this type can be manufactured without increasing the number of manufacturing steps.